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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Dual differential 3.3V LVPECL outputs which can be set independently for either 3.3V or 2.5V * 4:1 Input Mux: 1 differential input 1 single-ended input 2 crystal oscillator interfaces * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * TEST_CLK accepts LVCMOS or LVTTL input levels * Output frequency range: 30.625MHz to 640MHz * Crystal input frequency range: 12MHz to 40MHz * VCO range: 490MHz to 640MHz * Parallel or serial interface for programming feedback divider and output dividers * RMS phase jitter at 106.25MHz, using a 25.5MHz crystal (637kHz to 5MHz): 0.61ps (typical) * Supply voltage modes: LVPECL outputs (core/outputs): 3.3V/3.3V 3.3V/2.5V REF_CLK output (core/outputs): 3.3V/3.3V 3.3V/2.5V * 0C to 70C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS843034-01 is a general purpose, low IC S phase noise LVPECL synthesizer which can HiPerClockSTM generate frequencies for a wide variety of applications. The ICS843034-01 has a 4:1 input Multiplexer from which the following inputs can be selected: 1 differential input, 1 single-ended input, or one of two crystal oscillators, thus making the device ideal for frequency translation or generation. Each differential LVPECL output pair has an output divider which can be independently set so that two different frequencies can be generated. Additionally, each LVPECL output pair has a dedicated power supply pin so the outputs can run at 3.3V or 2.5V. The ICS843034-01 also supplies a buffered copy of the reference clock or crystal frequency on the single-ended REF_CLK pin which can be enabled or disabled (disabled by default). The output frequency can be programmed using either a serial or parallel programming interface. The ICS843034-01 has excellent <1ps phase jitter performance over the 637kHz - 5MHz integration range, thus making it suitable for use in Fibre Channel, SONET, and Ethernet/1Gb Ethernet applications. Example applications include systems which must support both FEC and non FEC rates. In 10Gb Fibre Channel, for example, you can use a 25.5MHz crystal to generate a 159.375MHz reference clock, and then switch to a 20.544MHz crystal to generate 164.355MHz for 66/64 FEC. Other applications could include supporting both Ethernet frequencies and SONET frequencies in an application. When Ethernet frequencies are needed, a 25MHz crystal can be used and when SONET frequencies are needed, the input MUX can be switched to select a 38.88MHz Crystal.
PIN ASSIGNMENT
M8 NB0 NB1 NB2 OE_REF OE_A OE_B VCC NA0 NA1 NA2 VEE
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 48-Pin LQFP 6 31 7mm x 7mm x 1.4mm 7 30 package body 8 29 Y Package 9 28 Top View 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843034AY -01
CLK nCLK nP_LOAD VCO_SEL M0 M1 M2 M3 M4 M5 M6 M7
ICS843034-01
XTAL_OUT1 XTAL_IN1 XTAL_OUT0 XTAL_IN0 TEST_CLK SEL1 SEL0 VCCA S_LOAD S_DATA S_CLOCK MR
VEE P_DIV VCCO_REF REF_CLK VCCO_B nFOUTB0 FOUTB0 VCCO_A nFOUTA0 FOUTA0 VCC TEST
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
BLOCK DIAGRAM
OE_A VCO_SEL XTAL_IN0 XTAL_OUT0
OSC
00
XTAL_IN1
OSC
XTAL_OUT1 CLK nCLK TEST_CLK SEL1 SEL0 P_DIV OE_B MR
01 PHASE DETECTOR VCO
0 1
/1 /2 /3 /4 /5 101 /6 /8 111 /16 / 000 001 010 011
FOUTA0 nFOUTA0 VCCO_A
10 11
1 /4 0 /8
001 011
VCCO_B FOUTB0 nFOUTB0
/M
101 111 /16 /
VCCO_REF REF_CLK
OE_REF S_LOAD S_DATA S_CLOCK nP_LOAD M8:M0 NA2:NA0 NB2:NB0
C
TEST
I
L
843034AY-01
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REV. C NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Nx bits can be hardwired to set the M divider and Nx output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M P The M value and the required values of M0 through M5 are shown in Table 3B to program the VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 20 M 25. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N NxP Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and Nx output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and Nx output divide values are latched on the HIGHto-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and Nx output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and Nx bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 0 1 TEST Output LOW S_Data, Shift Register Output Output of M divider CMOS Fout A0
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The ICS843034-01 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 490MHz to 640MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The ICS843034-01 supports either serial or parallel programming modes to program the M feedback divider and N output divider. The input divider P can only be changed using the P_DIV pin. It cannot be changed from the default /1 setting using the serial interface. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on the M, NA, and NB inputs are passed directly to the M divider and both N output dividers. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M and N dividers remain loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and
SERIAL LOADING
S_CLOCK
S_DATA
T1
T0
NB2
NB1 NB0
NA2
NA1
NA0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
S
t
H
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, P_DIV, NA0:NA2, NB0:NB2 nP_LOAD
M, N, P
t
S
t
H
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Input Input Input Power Input Input Power Output Output Power Output Power Output Power Input Pullup/ Pulldown Pullup Description M divider input. Data latched on LOW-to-HIGH trnsition of nP_LOAD Pulldown input. LVCMOS/LVTTL interfac levels. Pullup Determines output divider value as defined in Table 3C, Pulldown Function Table. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of REF_CLK output. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of FOUTA0, nFOUTA0 outputs. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of FOUTB0, nFOUTB0 outputs. LVCMOS/LVTTL interface levels. Core supply pins.
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3 4 5 6 7 8, 14 9, 10 11 12, 24 13 15, 16 17 18, 19 20 21 22 23 Name M8 NB0, NB1 NB2 OE_REF OE_A OE_B VCC NA0, NA1 NA2 VEE TEST FOUTA0, nFOUTA0 VCCO_A FOUTB0, nFOUTB0 VCCO_B REF_CLK VCCO_REF P_DIV
Pulldown Pullup Pullup
Determines output divider value as defined in Table 3C, Pulldown Function Table. LVCMOS/LVTTL interface levels. Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Differential output for the synthesizer. LVPECL interface levels. Output supply pin for FOUTA0, nFOUTA0. Differential output for the synthesizer. LVPECL interface levels. Output supply pin for FOUTB0, nFOUTB0. Reference clock output. LVCMOS/LVTTL interface levels. Output supply pin for REF_CLK. Input divide select. Float = /1 (default), 1 = / 4, 0 = /8. LVCMOS/LVTTL interface levels. Active High Master Reset. When logic HIGH, forces the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS/LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels. Analog supply pin.
25
MR
Input
Pulldown
26 27 28 29 30, 31 32 33, 34 35, 36 37 38
S_CLOCK S_DATA S_LOAD VCCA SEL0, SEL1 TEST_CLK XTAL_IN0, XTAL_OUT0 XTAL_IN1, XTAL_OUT1 CLK nCLK
Input Input Input Power Input Input Input Input Input Input
Pulldown Pulldown Pulldown
Pulldown Clock select inputs. LVCMOS/LVTTL interface levels. Pulldown Test clock input. LVCMOS/LVTTL interface levels. Cr ystal oscillator interface. Cr ystal oscillator interface. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input.VCC/2 default when left floating. Pulldown
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843034AY-01
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Type Input Description Parallel load input. Determines when data present at M5:M0 is loaded into M divider, and when data present at NA2:NA0 and Pulldown NB2:NB0 is loaded into the N output dividers. LVCMOS/LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS/LVTTL interface levels.
Number 39
Name nP_LOAD
40 41, 42, 43, 44, 45, 47, 48 46
VCO_SEL M0, M1, M2, M3, M4, M6, M7 M5
Input Input Input
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/LVTTL interface levels. Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance 5 Test Conditions Minimum Typical 4 51 51 7 12 Maximum Units pF k k
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REV. C NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL
AND
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Reset. Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. X X L L L H
MR H L L L L L L L
nP_LOAD X L H H H H H
M X Data Data X X X X X
N X Data Data X X X X X
S_LOAD
NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE P = /1 (P_DIV = FLOAT)
VCO Frequency (MHz) 500 * 550 * M Divide 20 * 22 * 32 M5 0 * 0 * 16 M4 1 * 1 * 8 M3 0 * 0 * 4 M2 1 * 1 * 2 M1 0 * 1 * 1 M0 0 * 0 * 1
625 25 0 1 1 0 0 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs *NX2 0 0 0 0 1 1 1 1
843034AY-01
*NX1 0 0 1 1 0 0 1 1
*NX0 0 1 0 1 0 1 0 1
N Divider Value 1 2 3 4 5 6 8 16
Output Frequency (MHz) Minimum 490 245 163.33 122.5 98 81.67 61.25 30.625 Maximum 640 320 213.33 160 128 106.67 80 40
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*NOTE: X denotes Bank A or Bank B
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V -0.5V to VCCO + 0.5V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO (LVCMOS) Outputs, IO (LVPECL) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_A = VCCO_B = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO_A, VCCO_B IEE ICCA VCCO_REF Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current REF_CLK Output Supply 3.135 2.375 Test Conditions Minimum 2.375 2.375 3.135 2.375 Typical 3.3 3.3 3.3 2.5 185 20 3.3 2.5 3.465 2.625 Maximum 3.465 3.465 3.465 2.625 Units V V V V mA mA V V
843034AY -01
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REV. C NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical Maximum Units
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_A = VCCO_B = 3.3V5% OR 2.5V5%, TA = 0C TO 70C)
Symbol Parameter VCO_SEL, SEL0, SEL1, MR, OE_REF, OE_A, OE_B, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, TEST_CLK, M0:M5, NX0:NX2 P_DIV VCO_SEL, SEL0, SEL1, MR, OE_REF, OE_A, OE_B, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, TEST_CLK, M0:M5, NX0:NX2 P_DIV TEST_CLK, P_DIV, MR, SEL[1:0], S_CLOCK, S_DATA, S_LOAD, nP_LOAD, OE_REF NA2, NB2, M1:M4, M6:M8 NB0, NB1, NA0, NA1, M5, OE_A, OE_B, VCO_SEL TEST_CLK, P_DIV, MR, SEL[1:0], S_CLOCK, S_DATA, S_LOAD, nP_LOAD, OE_REF NA2, NB2, M1:M4, M6:M8 NB0, NB1, NA0, NA1, M5, OE_A, OE_B, VCO_SEL VOH VOL Output High Voltage Output Low Voltage TEST; NOTE 1 TEST; NOTE 1
VIH
Input High Voltage
2
VCC + 0.3
V
VCC - 0.4
V
VIL
Input Low Voltage
-0.3
0.8
V
0.3 VCC = VIN = 3.465V 150
V A
IIH
Input High Current
VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V VCCO = 3.3V 5% VCCO = 2.5V 5% VCCO = 3.3V 5%, VCCO = 2.5V 5%
5
A
-5
A
IIL
Input Low Current
-150 2.6 1.8 0.5
A V V V
NOTE 1: Output terminated with 50 to VCCO_REF/2.
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_A = VCCO_B = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -150 -5 0.15 1.3 VCC - 0.85 Minimum Typical Maximum 150 150 Units A A A A V V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCCO_A = VCCO_B = 2.375V TO 3.465V, TA = 0C TO 70C
Symbol VOH V OL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO_x - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol Parameter XTAL_IN0, XTAL_OUT0 fIN Input Frequency XTAL_IN1, XTAL_OUT1 S_CLOCK Test Conditions Minimum 12 12 Typical Maximum 40 40 50 Units MHz MHz MHz
Rise Time S_CLOCK, S_DATA, S_LOAD 6 ns tR / tF NOTE: For the input cr ystal, CLK/nCLK and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 490MHz to 640MHz range. Using the minimum input frequency of 12MHz, valid values of M are 41 M 53. with input divider P = /1 (P_DIV = 00). Using the maximum frequency of 40MHz, valid values of M are 13 M 16.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 12 Test Conditions Minimum Typical Maximum 40 50 7 1 Units MHz pF mW Fundamental
TABLE 7A. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol Parameter FOUT t jit(O) t sk(o) t R / tF tS Output Frequency Phase Jitter, RMS (Random); NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD Output Duty Cycle Test Conditions Integration Range: 637kHz - 5MHz Measured @ the same Output Frequency 20% to 80% Minimum 30.625 0.61 50 200 5 5 5 5 5 5 50 1 700 Typical Maximum 640 Units MHz ps ps ps ns ns ns ns ns ns % ms
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843034AY -01
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REV. C NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Test Conditions Integration Range: 637kHz - 5MHz 20% to 80% 200 5 5 5 5 5 5 50 1 Minimum 30.625 0.71 50 700 Typical Maximum 640 Units MHz ps ps ps ns ns ns ns ns ns % ms
TABLE 7B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_A = VCCO_B = 2.5V5%, TA = 0C TO 70C
Symbol Parameter FOUT tjit(O) tsk(o) t R / tF tS Output Frequency Phase Jitter, RMS (Random); NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD Output Duty Cycle
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 7C. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_A = 3.3V5%, VCCO_B = 2.5V5%,TA = 0C TO 70C OR
VCC = VCCA = 3.3V5%, VCCO_A = 2.5V5%, VCCO_B = 3.3V5%,TA = 0C TO 70C
Symbol Parameter FOUT t jit(O) t sk(o) t R / tF tS Output Frequency Phase Jitter, RMS (Random); NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD Output Duty Cycle Test Conditions Integration Range: 637kHz - 5MHz 20% to 80% 20 0 5 5 5 5 5 5 50 1 Minimum 35 0.71 50 700 Typical Maximum 700 Units MHz ps ps ps ns ns ns ns ns ns % ms
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843034AY-01
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Integrated Circuit Systems, Inc.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 106.25MHZ
0 -10 -20 -30 -40 -50
Filter 106.25MHz
RMS Phase Jitter (Random) 637kHz to 5MHz = 0.61ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190
Raw Phase Noise Data
100 1k 10k
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Phase Noise Result by adding a Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
REV. C NOVEMBER 28, 2005
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ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
2.8V0.04V 2V
VCC , VCCA, VCCO_A, VCCO_B
Qx
SCOPE
VCC , VCCA VCCO_A, VCCO_B
Qx
SCOPE
LVPECL
nQx
LVPECL
VEE
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
1.65V5%
2.05V0.04V 1.25V5%
VCC , VCCA, VCCO_REF
SCOPE
Qx
VCC , VCCA
SCOPE
VCCO_REF VEE
Qx
LVCMOS
VEE
LVCMOS
-1.65V 5%
-1.25V 5%
3.3VCORE/3.3V REF_CLK OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V REF_CLK OUTPUT LOAD AC TEST CIRCUIT
VOH VREF VOL
nFOUTx FOUTx nFOUTy FOUTy
tsk(o)
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
PERIOD JITTER
843034AY-01
OUTPUT SKEW
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ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
nFOUTA0 FOUTA0
t PW
t
PERIOD
80% Clock Outputs
x 100%
80% VSW I N G
20% tR tF
20%
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843034-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F V CCA .01F 10 F 24
FIGURE 2. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS/LVTTL LEVELS
Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
CRYSTAL INPUT INTERFACE
The ICS843034-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 4 below were determined using a 25MHz, 18pF
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
ICS843034-01
ICS84332
Figure 4. CRYSTAL INPUt INTERFACE
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 5A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
FIGURE 5B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 5C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
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FIGURE 5D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER
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ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 6A and 6B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUTx and nFOUTx are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 6A. LVPECL OUTPUT TERMINATION
FIGURE 6B. LVPECL OUTPUT TERMINATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
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LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
close to ground level. The R3 in Figure 7B can be eliminated and the termination is shown in Figure 7C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 7A and Figure 7B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 7A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 7B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 7C. 2.5V LVPECL TERMINATION EXAMPLE
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ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843034-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843034-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 185mA = 641mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 641mW + 60mW = 701mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.701W * 42.1C/W = 99.5C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE JA
FOR
48-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8.
ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS843034-01
FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 9. JAVS. AIR FLOW TABLE
FOR
48 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843034-01 is: 5084
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FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
48 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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FEMTOCLOCKSTM MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Marking Package 48 Lead LQFP 48 Lead LQFP 48 Lead "Lead-Free" LQFP 48 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 11. ORDERING INFORMATION
Part/Order Number ICS843034AY-01 ICS843034AY-01T ICS843034AY-01LF ICS843034AY-01LFT ICS843034A01 ICS843034A01 ICS43034A01L ICS43034A01L
NOTE: Par ts that are ordred with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM and FEMTOCLOCKSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843034AY-01
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